
127
8008H–AVR–04/11
ATtiny48/88
Bit 2 – CPHA: Clock Phase
The settings of the Clock Phase bit (CPHA) determine if data is sampled on the leading (first) or
functionality is summarized below:
Bits 1:0 – SPR[1:0]: SPI Clock Rate Select 1 and 0
These two bits control the SCK rate of the device configured as a Master. SPR1 and SPR0 have
no effect on the Slave. The relationship between SCK and the oscillator clock frequency f
osc is
shown in the following table:
14.5.2
SPSR – SPI Status Register
Bit 7 – SPIF: SPI Interrupt Flag
When a serial transfer is complete, the SPIF Flag is set. An interrupt is generated if SPIE in
SPCR is set and global interrupts are enabled. If SS is an input and is driven low when the SPI is
in Master mode, this will also set the SPIF Flag. SPIF is cleared by hardware when executing the
corresponding interrupt handling vector. Alternatively, the SPIF bit is cleared by first reading the
SPI Status Register with SPIF set, then accessing the SPI Data Register (SPDR).
Bit 6 – WCOL: Write COLlision Flag
The WCOL bit is set if the SPI Data Register (SPDR) is written during a data transfer. The
WCOL bit (and the SPIF bit) are cleared by first reading the SPI Status Register with WCOL set,
and then accessing the SPI Data Register.
Bits 5:1 – Res: Reserved Bits
These bits are reserved and will always read zero.
Table 14-4.
CPHA Functionality
CPHA
Leading Edge
Trailing Edge
0
Sample
Setup
1
Setup
Sample
Table 14-5.
Relationship Between SCK and the Oscillator Frequency
SPI2X
SPR1
SPR0
SCK Frequency
00
0
f
osc/4
00
1
f
osc/16
01
0
f
osc/64
01
1
f
osc/128
10
0
f
osc/2
10
1
f
osc/8
11
0
f
osc/32
11
1
f
osc/64
Bit
7
654
32
10
SPIF
WCOL
–
SPI2X
SPSR
Read/Write
RR
R
R/W
Initial Value
0